TSMC's third-generation 3nm node is on track, and N3P will be mass-produced later this year
TSMC successfully started using the second-generation 3nm level process technology to produce chips in the fourth quarter of 2023, achieving the planned milestone. The company is currently preparing to mass produce performance enhanced N3P chips for this node. TSMC announced at the European Technology Symposium that this will take place in the second half of 2024.
The N3E process has entered mass production as scheduled, and the defect density is comparable to the N5 process during mass production in 2020. TSMC describes the yield of N3E as "great", and currently the only processor using N3E - Apple M4- has significantly increased the number of transistors and operating clock speed compared to M3 based on N3 technology.
A TSMC executive said at the event, "N3E started mass production as planned in the fourth quarter of last year. We have seen excellent production performance from our customers' products, so they have indeed entered the market as planned."
A TSMC executive said at the event, "N3E started mass production as planned in the fourth quarter of last year. We have seen excellent production performance from our customers' products, so they have indeed entered the market as planned."
The key detail of the N3E process is its simplification compared to TSMC's first generation N3 process (also known as N3B). By removing some layers that require EUV lithography and completely avoiding the use of EUV double patterning, N3E reduces production costs, widens the process window, and improves yield. However, these changes sometimes reduce transistor density and power efficiency, a trade-off that can be mitigated through design optimization.
Looking ahead, the N3P process provides optical scaling for N3E and also shows promising progress. It has passed the necessary qualification certification and shows yield performance close to N3E. The next evolution of TSMC's technology portfolio aims to improve performance by up to 4% or reduce power consumption by about 9% at the same clock speed, while also increasing the transistor density of hybrid design configuration chips by 4%.
N3P maintains compatibility with N3E's IP modules, design tools, and methods, making it an attractive choice for developers. This continuity ensures that most new chip designs (chips) are expected to transition from using N3E to N3P, leveraging the improved performance and cost efficiency of the latter.
The final production preparation work for N3P is expected to take place in the second half of this year, when it will enter the HVM (mass production) stage. TSMC expects chip designers to adopt it immediately. Given its performance and cost advantages, N3P is expected to be favored by TSMC customers, including Apple and AMD.
Although the exact launch date of N3P based chips is still uncertain, it is expected that major manufacturers such as Apple will use this technology in their processor series by 2025, including SoC for smartphones, personal computers, and tablets.
"We have also successfully delivered N3P technology," said TSMC executives. "It has been certified and its yield performance is close to N3E. (Process Technology) has also received product customers' wafers and production will begin in the second half of this year. Due to N3P's (PPA advantage), we expect most of the wafers on N3 to flow towards N3P."
Looking ahead, the N3P process provides optical scaling for N3E and also shows promising progress. It has passed the necessary qualification certification and shows yield performance close to N3E. The next evolution of TSMC's technology portfolio aims to improve performance by up to 4% or reduce power consumption by about 9% at the same clock speed, while also increasing the transistor density of hybrid design configuration chips by 4%.
N3P maintains compatibility with N3E's IP modules, design tools, and methods, making it an attractive choice for developers. This continuity ensures that most new chip designs (chips) are expected to transition from using N3E to N3P, leveraging the improved performance and cost efficiency of the latter.
The final production preparation work for N3P is expected to take place in the second half of this year, when it will enter the HVM (mass production) stage. TSMC expects chip designers to adopt it immediately. Given its performance and cost advantages, N3P is expected to be favored by TSMC customers, including Apple and AMD.
Although the exact launch date of N3P based chips is still uncertain, it is expected that major manufacturers such as Apple will use this technology in their processor series by 2025, including SoC for smartphones, personal computers, and tablets.
"We have also successfully delivered N3P technology," said TSMC executives. "It has been certified and its yield performance is close to N3E. (Process Technology) has also received product customers' wafers and production will begin in the second half of this year. Due to N3P's (PPA advantage), we expect most of the wafers on N3 to flow towards N3P."